View AT572D940HF_4342256.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Features
* DIOPSIS(R) Dual Core System Integrating an ARM926EJ-STM ARM(R) Thumb(R) Processor
Core and a mAgicV VLIW DSP of the Magic DSPTM family, optimized for Audio, Communication and Beam-forming Applications High Performance MagicV VLIW DSP - 1 GFLOPS - 1.6 Gops at 100 MHz - AHB Master Port, integrated DMA Engine and AHB Slave Port - Up to 10 Arithmetic Operations per Cycle (4 Multiply, 2 Add/subtract, 1 Add, 1 Subtract 40-bit Floating Point and 32-bit Integer) Allowing Single Cycle FFT Butterfly - Native Support for Complex Arithmetic and Vectorial SIMD Operations: One Complex Multiply with Dual Add/sub per Clock Cycle or Two Real Multiply and Two Add/sub or Simple Scalar Operations - 32-bit Integer and IEEE(R) 40-bit Extended Precision Floating Point Numeric Format - 16-port Data Register File: 256 Registers Organized in Two 128-register Banks - 5-issue predicated VLIW Architecture with Orthogonal ISA, Code Compression and Hardware Support for Code Efficient Software Pipeline Loops - 6 Accesses per Cycle Data Memory System (4 Accesses per Cycle for VLIW Operations + 2 Accesses per Cycle for DMA Transfers) supported by Flexible Addressing Capability - 2 Independent Address Generation Units Operating on a 64 Registers Address Register File Supporting Complex or Micro-Vectorial Accesses, and DSP features: Programmable Stride and Circular Buffers - 1.7 Mbits of On-chip SRAM: - 16 K x 40-bit Data Memory Locations (6 Memory Accesses per Cycle) - 8 K x 128-bit Dual Port Program Memory Location, Equivalent to ~50K DSP Assembler Instructions (typical) thanks to Code Compression and SW Pipelining - DMA Access to the External Program and Data Memory - Three Main Operating Modes: Run, Debug and Sleep Modes - User Mode and Privileged Interrupt Service Mode - Efficient Optimizing Assembler and C-Oriented Architecture: Allows Easy Exploitation of the Available Hardware Parallelism ARM926EJ-S ARM Thumb Processor - DSP instruction extensions - ARM Jazelle(R) Technology for Java(R) Acceleration - 16-KByte Data Cache, 16-KByte Instruction Cache, Write Buffer - 220MIPS at 200MHz - Memory Management Unit - EmbeddedICETM In-circuit Emulation, Debug Communication Channel Support Efficient ARM - DSP Interface through AHB master and slave ports, Memory Mapped Registers and Ports, Interrupt Lines and Semaphores Additional Embedded Memories - 32-KByte of internal ROM, two-cycle access at maximum bus speed - 48-KByte of internal SRAM, single-cycle access at maximum processor or bus speed External Bus Interface (EBI) - Supports SDRAM, Static Memory, SmartMedia(R) and NAND Flash, CompactFlash(R) USB - USB 2.0 Full Speed (12 Mbits per second) Host Double Port
*
DIOPSIS 940HF
ARM926EJ-S PLUS ONE GFLOPS DSP
AT572D940HF Preliminary Summary
*
* *
* *
NOTE: This is a summary document. The complete document is available under NDA. For more information, please contact your local Atmel sales office.
7010AS-DSP-07/07
*
*
*
*
*
*
* *
*
*
*
*
* *
- Dual On-chip Transceivers - Integrated FIFOs and Dedicated DMA Channels - USB 2.0 Full Speed (12 Mbits per second) Device Port - On-chip Transceiver, 2-Kbyte Configurable Integrated FIFOs - Two dedicated PDC channels Ethernet MAC 10/100 - Reduced Media Independent Interface (RMII) to Physical Layer - Integrated DMA channel AHB bus Matrix - Seven Masters and Five Slaves Handled - Boot Mode Select Option - Remap Command System Controller (SYSC) - Reset Controller - Periodic Interval Timer, Watchdog and Real-Time Timer Power Management Controller (PMC) - Very Slow Clock (32768Hz) Operating Mode - Software Programmable Power Optimization Capabilities - 3 to 20 MHz On-chip Oscillator and two PLLs - Four Programmable External Clock Signals Advanced Interrupt Controller (AIC) - Individually Maskable, Eight-level Priority, Vectored Interrupt Sources - Three External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected Three 32-bit Parallel Input/Output Controllers (PIO) - 96 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os - Input Change Interrupt Capability on Each I/O Line - Individually Programmable Open-drain, Pull-up resistor and Synchronous Output Twenty-three Peripheral Data Controller (PDC) Channels Debug Unit (DBGU) - 2-wire USART and support for Debug Communication Channel, Programmable ICE Access Prevention - Two dedicated PDC channels Four Synchronous Serial Controllers (SSC) - Two Independent Clock and Frame Sync Pair Signals for Each Receiver and Transmitter - IS Analog Interface Support, Time Division Multiplex Support - High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer - Two dedicated PDC channels for each SSC Three Universal Synchronous/Asynchronous Receiver Transmitters (USART) - Individual Baud Rate Generator, IrDA(R) Infrared Modulation/Demodulation - Support for ISO7816 T0/T1 Smart Card, Hardware and Software Handshaking, RS485 Support - Two dedicated PDC channels for each USART Two Master/Slave Serial Peripheral Interface (SPI) - 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects - Two dedicated PDC channels for each SPI One Three-channel 16-bit Timer/Counters (TC) - Three External Clock Inputs, Two multi-purpose I/O Pins per Channel - Double PWM Generation, Capture/Waveform Mode, Up/Down Capability Two Two-Wire Interfaces (TWI) - Master Mode Support, All Two-wire Atmel EEPROM's Supported Two CAN Interfaces - Fully compliant with CAN 2.0 Part A and 2.0 Part B
2
AT572D940HF Preliminary
7010AS-DSP-07/07
AT572D940HF Preliminary
* Multimedia Card Interface (MCI)
- Automatic Protocol Control and Fast Automatic Data Transfers with PDMA, MMC and SDCard Compliant
* IEEE 1149.1 JTAG Boundary Scan on All Digital Pins * Required Power Supplies:
- 1.1V / 1.2V for VDDCORE and VDDOSC - 3.3V for VDDPLLA - 3.3V for VDDIOP (Peripheral I/Os) and for VDDIOM (Memory I/Os) * Available in 324-ball CABGA Package
3
7010AS-DSP-07/07
1. Description
DIOPSIS 940HF is a Dual CPU Processor integrating a mAgicV VLIW DSP and an ARM926EJS RISC MCU, plus a total of 370 Kbytes SRAM. The system combines the flexibility of the ARM926TM RISC controller with the very high performance of the DSP. mAgicV is a high performance VLIW DSP of the Magic DSP family, delivering 1 Giga floatingpoint operations per second (GFLOPS) and 1.6 Gops at a clock rate of 100 MHz. It is equipped with an AHB master port and an AHB slave port for system-on-chip integration. It has 256 data registers, 64 address registers, 10 independent arithmetic operating units, 2 independent address generation units and a DMA engine. To sustain the internal parallelism, the data bandwidth among the Register File, the Operators and the Data Memory System, is 80 bytes/cycle. The Data Memory System is designed to transfer 28 bytes/cycle. For instance, mAgicV can produce one complete FFT butterfly per cycle by activating all the computing units. mAgicV operates on IEEE 754 40-bit extended precision floating-point and 32-bit integer numeric format for numerical computations, while internal memory accesses are supported by a powerful 16-bit MAGU (Multiple Address Generation Unit). It has also on-chip 16K x 40-bit 6-access/cycle data memory system and 8K x 128-bit dual port program memory locations. Efficient usage of the internal program memory is achieved through a general purpose code compression mechanism and software pipelining support of systematic loops. A C-oriented architecture and an optimizing assembler ease the user from the burden of dealing with the parallelism of the processor resources and significantly simplifies the code development. A rich library of C-callable DSP routines is available. The ARM926 embedded micro controller core is a member of the Advanced RISC Machines (ARM) family of general purpose 32-bit microprocessors, which offer high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and the related decode mechanism are much simpler than the micro programmed Complex Instruction Set Computers. This simplicity results in a high instruction throughput and impressive real-time interrupt response. The ARM926 supports 16-bit Thumb subset of the most commonly used 32-bit instructions. These are expanded at run time with no degradation of the system performance. This gives 16-bit code density (saving memory area and cost) coupled with a 32-bit processor performance. A rich set of peripherals and a 48 Kbytes internal memory provide a highly flexible and integrated system solution. The ARM926EJ-S supports the Jazelle technology for Java acceleration.
4
AT572D940HF Preliminary
7010AS-DSP-07/07
AT572D940HF Preliminary
2. Ball Configuration
Table 2-1.
Name A0/NBS0 A1/NBS2/NWR2 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16/SD_BA0 A17/SD_BA1 A18 A19 A20 A21 A_JCFG A_RTCK A_TCK A_TDI A_TDO A_TMS A_NTRST D0 D1 D2 D3 D4
AT572D940HF Ball Assignment (I/O: 191 balls)
Pin B2 C2 C1 D4 D3 D1 E4 E3 F6 G6 F3 H8 F2 F1 G3 H7 G1 G2 H6 H3 J8 H2 N16 M17 N17 M14 M16 N15 M13 H1 J7 J2 J1 K9 Name D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 M_NTRST M_TCK M_TDI M_TDO M_TMS NCS0 NCS1/SD_CS Pin K7 K5 K1 K2 K6 K8 L5 L1 L2 L4 L7 M3 L8 M4 M5 M6 N1 M7 N4 N5 P1 P3 P4 P5 R1 R2 R3 E16 F13 E15 E14 E17 F7 A6 Name NCS2 NCS3/SM_NCS NRD/NOE/CF_NOE NRST NWR0/NWE/CF_NWE NWR1/NBS1/CFIOR NWR3/NBS3/CFIOW PIOA0 PIOA1 PIOA2 PIOA3 PIOA4 PIOA5 PIOA6 PIOA7 PIOA8 PIOA9 PIOA10 PIOA11 PIOA12 PIOA13 PIOA14 PIOA15 PIOA16 PIOA17 PIOA18 PIOA19 PIOA20 PIOA21 PIOA22 PIOA23 PIOA24 PIOA25 PIOA26 Pin B7 E7 B6 J17 C6 D6 G7 F11 C11 A11 B11 H10 G10 D10 B17 A17 B16 A16 C15 H17 V15 U15 V16 T15 V17 T16 T17 U18 T18 R15 R18 H16 B9 D9 Name PIOA27 PIOA28 PIOA29 PIOA30 PIOA31 PIOB0 PIOB1 PIOB2 PIOB3 PIOB4 PIOB5 PIOB6 PIOB7 PIOB8 PIOB9 PIOB10 PIOB11 PIOB12 PIOB13 PIOB14 PIOB15 PIOB16 PIOB17 PIOB18 PIOB19 PIOB20 PIOB21 PIOB22 PIOB23 PIOB24 PIOB25 PIOB26 PIOB27 PIOB28 Pin G9 J9 A8 D8 B8 U8 L9 P9 R9 V9 L10 N10 V10 T10 P10 M10 N11 M11 L11 U12 T12 R12 N12 V13 U13 T13 P13 V14 R14 J10 H15 B12 A12 F9
5
7010AS-DSP-07/07
Table 2-1.
Name PIOB29 PIOB30 PIOB31 PIOC0 PIOC1 PIOC2 PIOC3 PIOC4 PIOC5 PIOC6 PIOC7 PIOC8 PIOC9 PIOC10
AT572D940HF Ball Assignment (I/O: 191 balls) (Continued)
Pin B10 A10 A9 D15 D14 C14 D13 C13 G12 F12 G13 F18 M18 L12 Name PIOC11 PIOC12 PIOC13 PIOC14 PIOC15 PIOC16 PIOC17 PIOC18 PIOC19 PIOC20 PIOC21 PIOC22 PIOC23 PIOC24 Pin L13 L18 K12 H13 G17 G18 G14 F17 H14 F16 E18 K14 K16 K17 Name PIOC25 PIOC26 PIOC27 PIOC28 PIOC29 PIOC30 PIOC31 PLL_RCA PLL_RCB SD_A10 SD_CK SD_CKE SD_NCAS SD_NRAS Pin K15 K11 K10 E12 D12 P16 P17 U2 P6 A7 B5 C5 A4 D5 Name SD_NWE TEST USBD_DM USBD_DP USBHA_DM USBHA_DP USBHB_DM USBHB_DP XIN XOUT X32EN X32IN X32OUT Pin B4 J18 N8 P8 R7 T7 U7 V7 U5 V5 N7 V2 V3
Table 2-2.
Name VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDIOM VDDIOM
AT572D940HF Ball Assignment (Power and Ground: 127 balls)
Pin F4 J4 L6 T2 M9 P11 T14 N13 L15 J13 H11 D16 E13 H9 E8 A2 D7 A5 Name VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOMP VDDIOMP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP Pin B3 E5 E1 G4 H4 J5 K3 M2 N3 P2 E9 G8 C10 D11 G11 A13 A15 C16 Name VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDOSC32 VDDOSCM Pin T9 V8 F14 G16 H18 J15 K13 L16 M12 N14 U17 P14 P12 U11 R10 V6 U4 R5 Name VDDPLLA GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin T3 D2 E2 F5 G5 H5 J6 J3 K4 L3 M1 N2 N6 R4 T1 T8 R8 N9
6
AT572D940HF Preliminary
7010AS-DSP-07/07
AT572D940HF Preliminary
Table 2-2.
Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND
AT572D940HF Ball Assignment (Power and Ground: 127 balls) (Continued)
Pin U10 V11 R11 V12 R13 U14 U16 P15 P18 N18 L14 J16 L17 K18 Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin J14 J12 H12 G15 F15 D18 D17 B15 B14 B13 C12 E11 F8 F10 Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin E10 C9 C8 C7 E6 A3 C4 U6 V4 M8 U9 T11 U1 A14 Name GND GND GND GND GND GND GND GND GND GND GNDOSC32 GNDOSCM GNDPLLA Pin R16 R17 M15 C18 C17 B18 C3 B1 T6 J11 T5 P7 U3
All pins not comprised in Table 2-1 and Table 2-2 are "not connected".
2.1
Pin Name Conventions
Pin names are built using the following structure: (functional block name) _ (activity level) (line name) (bus index) where: functional block name = name of the related functional block (when not a global function) activity level = "N" for low active lines; blank for high active lines line name = name of the function of the pin line bus index = number corresponding to the index when the pin line is an element of a bus
7
7010AS-DSP-07/07
3. Pin Description
Table 3-1.
Module AIC AIC AIC A JTAG A JTAG A JTAG A JTAG A JTAG A JTAG CAN CAN CAN CAN CF Logic CF Logic CF Logic CF Logic CF Logic CF Logic CF Logic DBGU DBGU EBI EBI EBI EBI EBI ETH
AT572D940HF Pin Description
Name EXT_IRQ0 EXT_IRQ2 M_MODE M_SIRQ0 M_SIRQ3 A_JCFG A_RTCK A_TCK A_TDI A_TDO A_TMS CAN0_RX CAN0_TX CAN1_RX CAN1_TX CF_NCE1CF_NCE2 CF_NOE CF_NWE CF_NIOR CF_NIOW CF_RNW CF_NCS0 CF_NCS1 DBG_RXD DBG_TXD A0 - A21 A22 - A25 D0- D31 NWAIT BMS E_RXER Function External Interrupt Request Interrupt Request from mAgicV Generic Interrupt Request from mAgicV ARM JTAG / Chip Boundary Scan select ARM JTAG Returned Test Clock ARM JTAG Test Clock ARM JTAG Test Data Input ARM JTAG Test Data Output ARM JTAG Test Mode Select CAN 0 bus Data in CAN 0 bus Data out CAN 1 bus Data in CAN 1 bus Data out CompactFlash Chip Enable CompactFlash Output Enable CompactFlash Write Enable CompactFlash IO Read CompactFlash IO Write CompactFlash Read Not Write CompactFlash Chip Select Debug Serial Line Data in Debug Serial Line Data out Address Bus Address Bus Data Bus External Wait Signal Boot Memory Select Ethernet RMII Receive Error bi-03 Type bi-03 bi-03 bi-03 in out-03 in in out-03 in bi-03 bi-03 bi-03 bi-03 bi-03 out-03 out-03 out-03 out-03 bi-03 bi-03 bi-03 bi-03 out-03 bi-03 bi-03 low low low low low low low output through PIO line output through PIO line input through PIO line output through PIO line 0 at reset output through PIO line 0 at reset Pulled-up input at reset input through PIO line input through PIO line 1! external boot selected 0! internal boot selected input through PIO line no pull-up resistor input through PIO line output through PIO line input through PIO line output through PIO line output through PIO line no pull-up resistor no pull-up resistor Active Level Notes input through PIO line output through PIO line output through PIO line internal pull-down resistor (ARM JTAG selected)
bi-03
8
AT572D940HF Preliminary
7010AS-DSP-07/07
AT572D940HF Preliminary
Table 3-1.
Module ETH ETH ETH ETH ETH ETH ETH ETH MCI MCI MCI M JTAG M JTAG M JTAG M JTAG M JTAG OSC OSC OSC OSC OSC PIO A PIO B PIO C PLL PLL PMC
AT572D940HF Pin Description (Continued)
Name E_TXD0 E_TXD1 E_TXEN E_REFCK E_CRSDV E_RXD0 E_RXD1 E_FCE100 E_MDIO E_MDCK MCCK MCCDA MCDA0MCDA3 M_NTRST M_TCK M_TDI M_TDO M_TMS XIN XOUT X32IN X32OUT X32EN PIOA0 PIOA31 PIOB0 PIOB31 PIOC0 PIOC31 PLL_RCA PLL_RCB A_CK Function Ethernet RMII Transmit Data Bus Ethernet RMII Transmit Enable Ethernet RMII Reference Clock Ethernet RMII Carrier Sense/Data Valid Ethernet RMII Receive Data Bus Ethernet RMII Force 100 Mb/s operation Ethernet RMII PHY Management Data Ethernet RMII PHY Management Clock Multimedia Card Clock Multimedia Card Command Multimedia Card Data mAgicV JTAG Test Reset mAgicV JTAG Test Clock mAgicV JTAG Test Data Input mAgicV JTAG Test Data Output mAgicV JTAG Test Mode Select Main Oscillator Quartz Main Oscillator Quartz Slow Clock Oscillator Quartz Slow Clock Oscillator Quartz Slow Clock Oscillator Enable Parallel Input/Output A Parallel Input/Output B Parallel Input/Output C PLL A Filter PLL B Filter ARM Clock Type bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 in in in out-03 in in out in out in bi-03 bi-03 bi-03 in in bi-03 to be left floating (test input) output through PIO line for test purpose high internal pull-up resistor (internal oscillator enabled) general purpose programmable I/Os or peripheral I/Os; Pulled-up input at reset general purpose programmable I/Os or peripheral I/Os; Pulled-up input at reset general purpose programmable I/Os or peripheral I/Os; Pulled-up input at reset no pull-up resistor no pull-up resistor no pull-up resistor high Active Level Notes output through PIO line output through PIO line input through PIO line input through PIO line input through PIO line output through PIO line through PIO line output through PIO line through PIO line through PIO line through PIO line
9
7010AS-DSP-07/07
Table 3-1.
Module PMC PMC SDRAMC SDRAMC SDRAMC SDRAMC SDRAMC SDRAMC SDRAMC SMC SMC SMC SMC SMC SMC SMC SM Logic SM Logic SPI
AT572D940HF Pin Description (Continued)
Name M_CK P_CK0-P_CK3 SDCK SD_CKE SD_NCS SD_BA0 SD_BA1 SD_NWE SD_NRAS SD_NCAS SD_A10 NCS0 - NCS3 NCS4 - NCS7 NWR0 - NWR3 NOE NRD NWE NBS0 - NBS3 SM_NOE SM_NWE SPI0_MOSI Function mAgicV Clock Programmable Clock SDRAM Clock Output SDRAM Clock Enable SDRAM Chip Select SDRAM Bank Select SDRAM Write Enable Row and Column Address Strobe SDRAM Bus Address bit 10 Chip Select Signal Chip Select Signal Write Signal Output Enable Read Signal Write Enable Byte Select SmartMedia Output Enable SmartMedia Write Enable SPI 0 Master Out/Slave In data Type bi-03 bi-03 out-03 out-04 out-03 out-03 out-04 out-04 out-04 out-03 bi-03 out-03 out-03 out-03 out-03 out-03 bi-03 bi-03 bi-03 low low low low low low low low low 1 at reset; 1 at reset output through PIO line 1 at reset 1 at reset 1 at reset 1 at reset 1 at reset output through PIO line output through PIO line through PIO line SPI SLV ! data input SPI MST ! data output through PIO line SPI SLV ! data output SPI MST ! data input low through PIO line SPI SLV ! CS Input SPI MST ! CS 0 Output output through PIO line SPI SLV ! n.a. SPI MST ! CS 3, 2, 1 Outputs through PIO line SPI SLV ! clock input SPI MST ! clock output low low high low Active Level Notes output through PIO line for test purpose output through PIO line
SPI
SPI0_MISO
SPI 0 Master In/Slave Out data
bi-03
SPI
SPI0_NCS0
SPI 0 Input/Output Chip select
out-03
SPI
SPI0_NCS1 SPI0_NCS3
SPI 0 Output Chip Selects
bi-03
low
SPI
SPI0_CK
SPI 0 Serial clock
bi-03
10
AT572D940HF Preliminary
7010AS-DSP-07/07
AT572D940HF Preliminary
Table 3-1.
Module SPI
AT572D940HF Pin Description (Continued)
Name SPI1_MOSI Function SPI 1 Master Out/Slave In data Type bi-03 Active Level Notes through PIO line SPI SLV ! data input SPI MST ! data output through PIO line SPI SLV ! data output SPI MST ! data input low through PIO line SPI SLV ! CS Input SPI MST ! CS 0 Output output through PIO line SPI SLV ! n.a. SPI MST ! CS 3, 2, 1 Outputs through PIO line SPI SLV ! clock input SPI MST ! clock output output through PIO line input through PIO line through PIO line through PIO line through PIO line through PIO line output through PIO line input through PIO line through PIO line through PIO line through PIO line through PIO line output through PIO line through PIO line
SPI
SPI1_MISO
SPI 1 Master In/Slave Out data
bi-03
SPI
SPI1_NCS0
SPI 1 Input/Output Chip select
out-03
SPI
SPI1_NCS1 SPI1_NCS3
SPI 1 Output Chip Selects
bi-03
low
SPI
SPI1_CK
SPI 1 Serial clock Synchronous Serial Controller 0 Data Out Synchronous Serial Controller 0 Data In Synchronous Serial Controller 0 Transmit Frame Clock Synchronous Serial Controller 0 Receive Frame Clock Synchronous Serial Controller 0 Transmit Bit Clock Synchronous Serial Controller 0 Receive Bit Clock Synchronous Serial Controller 1 Data Out Synchronous Serial Controller 1 Data In Synchronous Serial Controller 1 Transmit Frame Clock Synchronous Serial Controller 1 Receive Frame Clock Synchronous Serial Controller 1 Transmit Bit Clock Synchronous Serial Controller 1 Receive Bit Clock Synchronous Serial Controller 2 Data Out Synchronous Serial Controller 2 Transmit Frame Clock
bi-03
SSC SSC SSC SSC SSC SSC SSC SSC SSC SSC SSC SSC SSC SSC
SSC0_TXD SSC0_RXD SSC0_TF SSC0_RF SSC0_TK SSC0_RK SSC1_TXD SSC1_RXD SSC1_TF SSC1_RF SSC1_TK SSC1_RK SSC2_TXD SSC2_TF
bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03
11
7010AS-DSP-07/07
Table 3-1.
Module SSC SSC SSC SSC SSC SSC SSC SSC SSC SSC SYSC TC TC TC TC TC TC TC TC TC TST TWI TWI TWI TWI USBD USBD USBH
AT572D940HF Pin Description (Continued)
Name SSC2_RF SSC2_TK SSC2_RK SSC2_RXD SSC3_TXD SSC3_RXD SSC3_TF SSC3_RF SSC3_TK SSC3_RK NRST TC_OUT_A0 TC_OUT_A1 TC_OUT_A2 TC_OUT_B0 TC_OUT_B1 TC_OUT_B2 TC_IN_0 TC_IN_1 TC_IN_2 TEST TW0_D TW0_CK TW1_D TW1_CK USBD_DM USBD_DP USBHA_DM Function Synchronous Serial Controller 2 Receive Frame Clock Synchronous Serial Controller 2 Transmit Bit Clock Synchronous Serial Controller 2 Receive Bit Clock Synchronous Serial Controller 2 Data In Synchronous Serial Controller 3 Data Out Synchronous Serial Controller 3 Data In Synchronous Serial Controller 3 Transmit Frame Clock Synchronous Serial Controller 3 Receive Frame Clock Synchronous Serial Controller 3 Transmit Bit Clock Synchronous Serial Controller 3 Receive Bit Clock Chip Reset Timer Counter A out 0 Timer Counter A out 1 Timer Counter A out 2 Timer Counter B out 0 Timer Counter B out 1 Timer Counter B out 2 Timer Counter in 0 Timer Counter in 1 Timer Counter in 2 Test Mode Select Two Wire 0 Data Two Wire 0 Clock Two Wire 1 Data Two Wire 1 Clock USB Device Port Data USB Device Port Data + USB Host Port A Data Type bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 in bi-03 bi-03 bi-03 bi-03 usb-bi usb-bi usb-bi high low Active Level Notes through PIO line through PIO line through PIO line input through PIO line output through PIO line input through PIO line through PIO line through PIO line through PIO line through PIO line open drain through PIO line bidirectional through PIO line bidirectional through PIO line bidirectional through PIO line bidirectional through PIO line bidirectional through PIO line input through PIO line input through PIO line input through PIO line pull-down resistor (Functional Mode selected) bidirectional through PIO line bidirectional through PIO line bidirectional through PIO line bidirectional through PIO line
12
AT572D940HF Preliminary
7010AS-DSP-07/07
AT572D940HF Preliminary
Table 3-1.
Module USBH USBH USBH USART USART USART USART USART USART USART USART USART USART USART USART USART USART USART Power Power Power Power Power Power Ground Ground Ground Ground
AT572D940HF Pin Description (Continued)
Name USBHA_DP USBHB_DM USBHB_DP USART0_RXD USART0_TXD USART0_SCK USART0_CTS USART0_RTS USART1_RXD USART1_TXD USART1_SCK USART1_CTS USART1_RTS USART2_RXD USART2_TXD USART2_SCK USART2_CTS USART2_RTS VDDCORE VDDIOP VDDIOM VDDOSC32 VDDOSCM VDDPLLA GND GNDOSC32 GNDOSCM GNDPLLA Function USB Host Port A Data + USB Host Port B Data USB Host Port B Data + USART 0 Data in USART 0 Data out USART 0 Serial clock USART 0 Clear to send USART 0 Request to send USART 1 Data in USART 1 Data out USART 1 Serial clock USART 1 Clear to send USART 1 Request to send USART 2 Data in USART 2 Data out USART 2 Serial clock USART 2 Clear to send USART 2 Request to send Core power supply Peripherals I/O Lines Power Supply EBI I/O Lines Power Supply 32KHz Oscillator Power Supply Main Oscillator PLLB Power Supply PLLA power supply Core and IO Ground 32KHz Oscillator Ground Main Oscillator PLLB Ground PLLA Ground Type usb-bi usb-bi usb-bi bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 Power Power Power Power Power Power Ground Ground Ground Ground input through PIO line bidirectional through PIO line bidirectional through PIO line for synchronous mode only input through PIO line output through PIO line input through PIO line bidirectional through PIO line bidirectional through PIO line for synchronous mode only input through PIO line output through PIO line input through PIO line bidirectional through PIO line bidirectional through PIO line for synchronous mode only input through PIO line output through PIO line 1.1V / 1.2V 3.3V 3.3V 1.1V / 1.2V 1.1V / 1.2V 3.3V Active Level Notes
13
7010AS-DSP-07/07
4. Block Diagram
Figure 4-1. AT572D940HF Architecture
ARM926EJ-S
ARM JTAG ICE
Instruction Cache 16K bytes MMU Data Cache 16K bytes
D0-D31 A0/NBS0 A1/NBS2/NWR2 A2-A15/A18-A21 A16/SD_BA0 A17/SD_BA1 NCS0 NCS1/SD_NCS NCS2 NCS3/SM_NCS NRD/NOE/CF_NOE NWR0/NWE/CF_NWE NWR1/NBS1/CF_NIOR NWR3/NBS3/CF_NIOW SD_CK SD_CKE SD_NRAS-SD_NCAS SD_NWE SD_A10 A22-A25/CF_RNW NCS4/CF_NCS0 NCS5/CF_NCS1 CF_NCE1 CF_NCE2 NCS6/SM_NOE NCS7/SM_NWE NWAIT BMS
A_JCFG A_TDI A_TMS A_RTCK A_TCK A_TDO
EBI
CompactFlash SmartMedia NAND Flash
TCM IF
NRST TEST VDDCORE POR
BIU
I D
SYSC
RST CNTL PIT RTT WDG
I
D
ITCM DTCM
X32IN X32OUT X32EN XIN XOUT PLL_RCA PLL_RCB A_CK M_CK PCK0-PCK3
32K OSC
Fast SRAM 48 Kbytes
SDRAM CNTL
MAIN OSC PLL A PLL B
Fast ROM 32 Kbytes
Static Memory CNTL
PIO
PMC
Peripheral Bridge
EXT_IRQ0-EXT_IRQ2
AIC PDC 7x5 AHB MATRIX
DMA
FIFO
TRANSCEIVER
USBHA_M USBHA_P USBHB_M USBHB_P
USB HOST
DBG_TXD DBG_RXD
DBGU
PDC
USARTx_TXD USARTx_RXD USARTx_SCK USARTx_CTS USARTx_RTS
USART 0-1-2
PDC
mAgic JTAG
M_TDI M_TMS M_NTRST M_TCK M_TDO
SPIx_MOSI SPIx_MISO SPIx_NCS0 SPIx_NCS1-SPIx_NCS3 SPIx_CK
SPI 0-1
PDC
APB
mAgic
+ memories
M_MODE M_SIRQ0-M_SIRQ3
PIOx
PIO A-B-C Controllers
DMA
FIFO RMII
TWx_CK TWx_D
TWI 0-1
PDC
ETH MAC
SSCx_RXD SSCx_TXD SSCx_TF SSCx_TK SSCx_RF SSCx_RK
E_MDIO E_MDC E_FCE100 E_RXER E_TX0-E_TX1 E_TXEN E_REFCK E_CRSDV E_RX0-E_RX1
PIOx
SSC 0-1-2-3
PDC
Timer Counter
TC0 TC1 TC2
MCCK MCCDA MCDA0-MCDA3
MCI
PDC
TC_OUT_A_0 TC_OUT_A_1 TC_OUT_A_2 TC_OUT_B_0 TC_OUT_B_1 TC_OUT_B_2 TC_IN_0 TC_IN_1 TC_IN_2
CANx_RX CANx_TX
FIFO CAN 0-1 USB DEVICE
TRANSCEIVER
USBD_M USBD_P
14
AT572D940HF Preliminary
7010AS-DSP-07/07
AT572D940HF Preliminary
5. Architectural Overview
DIOPSIS 940 HF (also named D940HF) is a high performance dual-core processing platform for audio, communication and beam-forming applications, integrating a floating-point DSP (mAgicV VLIW DSP) and an ARM926EJ-S Reduced Instruction Set Computer (RISC). The D940HF is optimally suited for floating point applications with a significant need for complex domain computations like FFT and frequency domain phase-shift algorithms, requiring high dynamic range and maximum numerical precision. The D940HF combines the flexibility of the ARM926 RISC controller with the very high performance of the DSP oriented VLIW architecture of mAgicV.
5.1
System management
The availability of a standard RISC on-chip lowers software development effort for non critical and control segments of the application. ARM926 features an MMU for virtual memory and sophisticated memory protection, making it an ideal platform for operating systems such as WinCE or Linux. This leaves mAgicV fully available for the numerically intensive part of the application. The synchronization between the two processors can be either based on interrupts or on software polling on semaphores. The ARM926 is the D940HF master processor. The bootstrap sequence of the D940HF starts from the bootstrap of the ARM926 from its internal ROM or external non-volatile memory. The ARM then boots mAgicV from a non-volatile memory. After bootstrap the D940HF can start its normal operations. The DSP side of many applications can be implemented on the D940HF by using only the internal memory. In fact, the program memory size of 8K by 128-bit coupled with the availability of the general purpose code compression and software pipelining of systematic loops, gives an equivalent on-chip program memory size of about 24K cycles, corresponding to ~50K DSP assembler instructions (typical).
5.2
AMBA Architecture
The architecture is based on AMBATM bus: the multilayer AHB matrix and the APB. The AHB matrix consists of seven masters: 0. ARM926 Instruction 1. ARM926-Data 2. Peripheral Data Controller (PDC) 3. mAgicV 4. USB Host 5. Ethernet MAC 10/100 6. mAgicV JTAG and of five slaves: 0. ARM926 SRAM 1. ARM926 ROM 2. mAgicV Registers and Memories + USB Host Registers 3. The External Bus Interface 4. The AHB-APB bridge
15
7010AS-DSP-07/07
5.3
mAgicV VLIW DSP Processor
The mAgicV VLIW DSP is the numeric processor of the D940HF. It operates on IEEE 754 40-bit extended precision floating-point and 32-bit integer numeric format. The main components of the DSP subsystem are the core processor, the on-chip memories, the DMA engine and its AHB master and slave interfaces. The operators block, the register file, the multiple address generation unit and the program decoding and sequencing unit are the computing part of the core processor. A short description of each block is given in the following paragraphs. Figure 5-1. mAgicV DSP Block Diagram
AHB layer-y AHB layer-x
Multi Layer AHB System Bus
2-port, 8Kx128-bit, VLIW Program Memory VLIW Decompressor Flow Controller, VLIW Decoder Program Condition Status Instruction Counter Generation Register Decoder
AHB Master DMA Engine
AHB Slave, e.g. DMA Target
16-port 256x40-bit Data Register File System
4-address/cycle Multiple DSP Address Generation Unit 16 multi-field Address Register File
6-access/cycle Data Memory System 16Kx40-bit
Operators: 10-float ops/cycle
5.3.1
RISC-like VLIW DSP mAgicV is a Very Long Instruction Word engine, but from an user point of view, it works like a RISC machine by implementing triadic computing operations on data coming from the register file, and data move operations between the local memories and the register file. The operators are pipelined for maximum performance. The pipeline depth depends on the operator used. The scheduling and parallelism operations are automatically defined and managed at compile time by the assembler-optimizer, allowing efficient code execution. The architecture is designed for efficient C-language support. 16-port, 256x40-bit Data Register File System In order to provide optimal data bandwidth and to give the best support to the RISC-like programming model, mAgicV arithmetic computations are supported by a 16-ported, 256x40-bit entries, Data Register File System. The Data Register File can also be viewed as a complex 128-entry register file. It can be used as a complex register file (real + imaginary part), or as a dual register file for vectorial operations. When performing scalar instructions on the real domain, the register file can be used as an ordinary 256 register file. Both the odd and even sides of the register file are 9-ported (4-read ports and 4-write ports for computing/move operations + 1 port for independent debug access), making a total of 16 I/O ports available for the data
5.3.2
16
AT572D940HF Preliminary
7010AS-DSP-07/07
AT572D940HF Preliminary
move to and from the operators block and the memory, plus the ports for the debug accesses. The total data bandwidth between the register file, the operators block and the data memory is 80 bytes per clock cycle, thus avoiding bottlenecks in the data flow inside the VLIW core. The Operators block, the Data Register File, the Multiple Address Generation Unit and the FlowController are the computing part of the core processor. The core is integrated with a 6access/cycle, 16Kx40-bit on-chip Data Memory System and a 2-port, 8Kx128-bit on-chip VLIW Program Memory. The mAgicV VLIW DSP is equipped with an integrated AHB master and a DMA Engine plus an AHB Slave interface. 5.3.3 DSP Operators Block The Operators Block contains the hardware that performs arithmetical operations. It works on 32-bit signed integers and IEEE 754 extended precision 40-bit floating-point data. The Operators Block is composed of four integer/floating point multipliers, an adder, a subtractor and two add-subtract integer/floating point units; moreover, it has two shift/logic units, a Min/Max operator and two seed generators for efficient division and inverse square root computation. The operators block is arranged in order to natively support complex arithmetic (single cycle complex multiply or multiply and add), fast FFT (single cycle butterfly computation) and vectorial computations (e.g. for Audio Stereo Channel support). The peak performance of mAgicV is achieved during single cycle FFT butterfly execution, when mAgicV delivers 10 floating-point operations per clock cycle. 6-port On-Chip Data Memory System The Data Memory System of mAgicV contains 16K*40-bit on-chip memory locations supporting up to 6 accesses/cycle. 4-accesses/cycle are reserved to the activities driven by the Multiple Address Generation unit of mAgicV: these accesses are reserved to the computing part of the core. 1 access/cycle is assigned to serve the DMA activity launched by the core itself, through mAgicV AHB master port. 1 additional access/cycle can be simultaneously requested by external devices through mAgicV AHB slave port (e.g for data exchange with the interfaces of the ADC and the DAC converters). The Data Memory System is physically organized using two banks (assigned to even and odd addresses) of quadruple-port memories. The total bandwidth available is 28 bytes/cycle; for the computing part of the core it is 20 bytes per clock cycle, allowing full speed implementation of numerically intensive algorithms (e.g. complex FFT and FIR), plus 8 bytes/cycle assigned to the AHB master and slave interfaces. Multiple DSP Address Generation Unit (MAGU) The core can access vectorial and single data stored in the Data Memory. Accessing complex data is equivalent to accessing vectorial data (a pair of consecutive even and odd addresses pointing to the pair of banks). In vectorial mode, the Multiple Address Generation Unit (MAGU) is able to generate up to 4 addresses/cycle: two pairs of vectorial addresses, one to access the Data Memory System for reading a consecutive pair of memory locations and one address for writing a consecutive pair of memory locations. The MAGU can also generate any combination of two scalar accesses to the Data Memory System (Read-Read, Read-Write, Write-Write of any pair of single location accesses), or the combination of one vectorial access and one scalar access. The MAGU supports linear addressing and DSP oriented features like stride access and circular buffers. The address generation unit is supported by 16 multi field addressing registers each one composed of 4 16-bit individually addressable registers, for a total of 64 signed 16-bit integer registers. Registers named A0-A15 are used for the storage of pointers, while registers M0-M15 are for the 16-bit integer modifiers. For circular buffers, S0-S15 store the Start Addresses of the buffers, and L0-L15 are initialized with the circular buffer lengths. The MAGU
5.3.4
5.3.5
17
7010AS-DSP-07/07
can also be used to perform 16-bit signed integer arithmetic operations in parallel with the activities of the operators block (40-bit floating point and 32 signed integer operations). The MAGU also performs the loop control computations needed to verify if the end of a loop is reached. 5.3.6 Flow Controller The Flow Controller is dedicated to program address generation, conditioning, predication and software pipelining of systematic loops. The Program Address Generation Unit is devoted to control the correct Program Counter generation according to the program flow. It generates addresses for linear code execution as well as for non-sequential program flow. The Condition Generation Unit combines the flags generated by the operators and by the MAGU to produce complex conditions flags used to control the program execution. The Program Address Generation Unit also allows to perform conditioned and unconditioned branch instructions, loops, call to subroutines and return from subroutines. Dual-Port On-Chip Program Memory The Program Memory stores the VLIW program to be executed by mAgicV. It is 8K words by 128-bit dual port memory. One port is driven by the Flow Controller to fetch the compressed VLIW word. The other port is accessed by the DMA engine, supported by the AHB master interface, or by the external devices through mAgicV AHB slave port. 5 predicated VLIW Issues At every cycle, a typical mAgicV VLIW instruction activates 5 issues named AGU0, AGU1, ADD, MULT and FLOW. The first two issues are associated to the pair of independent Address Generation Units in the MAGU. The third issue drives the Arithmetic Add/Subtract section of the Operators Block, the fourth drives the Multiplier section, and the last issue drives the Flow Controller. Each issue is predicated by a specific predication field, for conditional execution without pipeline breaking penalties. Using different instruction formats, the VLIW word can also contain initialization requests for the DMA engine, single cycle loading of multiple immediate values and other service instructions. Software pipelining Software pipelining of systematic loops is optimally supported by a dedicated engine which activates the VLIW issues only during the appropriate loop iterations. This mechanism is designed to reach optimal program memory usage of the DSP library and completes the general purpose Code Compression scheme. Program Compression The mAgicV VLIW architecture is natively designed for optimal program density. Moreover, a program compression scheme allows an average additional program compression between 2 and 3. Therefore, more than 10 issues are stored for each 128 bit program memory locations. A high Program Memory density is achieved thanks to the combined effect of Program Compression and Software Pipelining. The DSP side of many applications can be implemented on the D940HF using only the internal memory. In fact, the 8K by 128-bit program memory size provides, with code compression, ~50K DSP assembler instructions stored on-chip (typical). For DSP libraries, the density is even greater where software pipelining is activated. If the on-chip program memory is not large enough to contain the full DSP application, a DMA must be launched to refill the dual-port Program Memory. Thanks to the program compression, the program memory refill does not stall the activities of the DSP core.
5.3.7
5.3.8
5.3.9
5.3.10
18
AT572D940HF Preliminary
7010AS-DSP-07/07
AT572D940HF Preliminary
5.3.11 mAgicV AHB master interface mAgicV VLIW DSP is equipped with an AHB master which supports mAgicV DMA engine. AHB DMA on Data Memory System At every cycle, one port of the on-chip Data Memory System is reserved to fetch/store the activity driven by the DMA Engine. The DMA to the external memories or to the other devices mapped on the AHB System Bus is supported by mAgicV AHB master interface. The DMA engine can generate stride access to the external memory. The DMA transfers to and from the on-chip Memory can be executed in parallel with the full speed core instructions execution with zero-overhead and without the intervention of the core processor, except for initiating it. AHB DMA on Program Memory The on-chip Program Memory of mAgicV is a dual port. One port is reserved to the instruction fetch and the other to the DMA engine. In parallel with the activities of the core, a DMA can be activated between the external memories and the other devices mapped on the AHB System Bus. mAgicV AHB slave interface External AHB masters, like ARM and JTAG can access the memories and the registers of mAgicV DSP through mAgicV AHB slave interface. In Debug mode (see Section 5.3.15.3 below) all the internal resources are memory mapped, while in run mode or sleep mode access restrictions apply (see Section 5.3.15.1 and Section 5.3.15.2 below). At every cycle, one port of the Data Memory System is reserved to read/store accesses performed through the AHB slave interface. Example of usage: data sampled by AD Converters can be written inside the mAgicV Data Memory in parallel to the DMA (through the master port) and the VLIW operations. Operating Modes of mAgicV mAgicV VLIW DSP can operate in three operating modes: Run mode, Sleep mode and Debug mode. The access allowed to the different resources through the AHB slave port depends on the status mode: Run Mode In Run Mode, a mAgicV VLIW program is under execution. mAgicV can access external resources through its AHB master interface. Control and status registers are visible. One port of the Data Memory System is accessible through the AHB Slave port. 5.3.15.2 Sleep Mode In Sleep Mode, the AHB Master and Slave port and the DMA engine are still active. However, only "non-destructive access paths" are guaranteed through the AHB slave interface. Control and Status registers are active. Data and Address Registers are frozen (readable but not writable). 5.3.15.3 Debug Mode In Debug Mode, mAgicV suspends its execution (if any) and debug paths are allowed. Data and Program memories are readable. Data and Address registers are readable. Pipeline registers are frozen. Any external master, like JTAG or the ARM can access the internal resources of mAgicV DSP for debug purpose. The ability of the ARM to access internal mAgicV resources in Debug Mode can be used for initialization and also for debugging purposes. By accessing the Command Register, the ARM can change the operating status of the DSP (Run/System Mode),
5.3.12
5.3.13
5.3.14
5.3.15
5.3.15.1
19
7010AS-DSP-07/07
initiate DMA transactions, force single or multiple step execution, or simply read the DSP operating status. 5.3.16 User/ Privileged Interrupt Mode During Run mode, mAgicV can execute either in User mode or in Privileged Interrupt Mode. ARM<->mAgicV Interrupts In order to allow a tight coupling between the operations of mAgicV and the ARM at run time, they can exchange synchronization signals, based on interrupts.
5.3.17
20
AT572D940HF Preliminary
7010AS-DSP-07/07
AT572D940HF Preliminary
5.4 ARM926 Processor
The ARM926 is a member of ARM9TM family of general purpose microprocessors. The ARM926 is targeted at multi-tasking applications where full memory management, high performance and low power are important. The ARM926 supports the 32-bit ARM and 16-bit THUMB instruction sets, enabling the user to trade off between high performance and high code density. The ARM926 includes features for efficient execution of Java byte codes. The ARM926 supports the ARM debug architecture and includes logic to assist both the hardware and the software debug. The ARM926 provides an integer core that supports the DSP instruction set extension. The ARM926 supports virtual memory addressing through its standard ARM v4 and v5 memory management unit (MMU). The ARM926 provides two independent AHB master interfaces for data and instruction. The ARM926 provides two independent Tightly Coupled Memory (TCM) interfaces. The ARM926 implements ARM architecture version 5TEJ with 5 stage pipeline. The ARM926 embeds 16-Kbyte Data Cache and 16-Kbyte Instruction Cache. 5.4.1 ARM Memories The ARM926 memories consist of: * 32Kbyte ROM selectable as boot memory * 48Kbyte Fast SRAM - Single Cycle Access at full bus speed - Supports ARM926EJ-S TCM interface at full processor speed - D-TCM and I-TCM programmable size 5.4.2 Arm Boot The system always boots at address 0x0. The memory layout can be configured with two parameters to ensure a maximum number of possibilities for booting. REMAP allows the user to lay out the first internal SRAM bank to 0x0 to ease development. This is done by software once the system has booted for each Master of the Bus Matrix. When REMAP = 1, BMS is ignored. Refer to the Bus Matrix Section for more details. When REMAP = 0, BMS allows the user, at ones convenience, to lay out the ROM or an external memory to 0x0. This is done via hardware at reset. Note that Memory blocks not affected by these parameters can always be seen at their specified base addresses. The complete memory map is presented in Table 5-1 to Table 5-4. The Bus Matrix manages a boot memory that depends on the level on the BMS pin at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is reserved for this purpose. If BMS is detected at 1, the boot memory is the embedded ROM. If BMS is detected at 0, the boot memory is the memory connected on the Chip Select 0 of the External Bus Interface.
21
7010AS-DSP-07/07
5.4.2.1
BMS = 1, Boot on Embedded ROM The system boots using the Boot Program from the embedded ROM following the steps listed below: Checks the presence of an SD card with a boot.bin file in the main dir: If the file is found: * Downloads the code in internal SRAM at 0x300000 * Executes Remap command * Runs SD Boot code If the file is not found, downloads the code from the SPI DataFlash(R): * Downloads the code in internal SRAM at 0x300000 * Checks the presence of a valid code on the first six word * Executes Remap command * Runs DataFlash Boot code In case no valid program is detected in the external SPI DataFlash: - - Activates a Boot uploader enabling small monitor functionalities (read/write/run) interface with the SAM-BATM application Performs an automatic detection of the communication link: Serial communication on a DBGU (XModem protocol) USB Device Port (CDC Protocol)
5.4.2.2
BMS = 0, Boot on External Memory * Boot on slow clock (32,768 Hz) * Boot with the default configuration for the Static Memory Controller, byte select mode, 32-bit data bus, Read/Write controlled by Chip Select, allows boot on 32-bit non-volatile memory. The customer-programmed software must perform a complete configuration. To speed up the boot sequence when booting at 32 kHz EBI CS0 (BMS=0), the user must take the following steps: 1. Program the PMC (main oscillator enable or bypass mode). 2. Program and start the PLL. 3. Reprogram the SMC setup, cycle, hold, mode timings registers for CS0 to adapt them to the new clock Peripheral Data Controller (PDC). 4. Switch the main clock to the new value.
5.5
Peripheral Data Controller (PDC)
The PDC acting as an AHB master controls the data transfer between on chip peripherals: USARTs, SPIs, SSCs, MCI, DBGU, TWIs and the on- and off-chip memories. This leaves both the processors free of the overhead related to this function.
5.6
USB Host
The USB host acting as an AHB master controls the data exchange between the two USB host channels (port A and port B) and the ARM Internal RAM or the external memories. The USB Host Port features:
22
AT572D940HF Preliminary
7010AS-DSP-07/07
AT572D940HF Preliminary
- Compliance with Open HCI Rev 1.0 specification - Compliance with USB V2.0 Full-speed and Low-speed Specification - Supports both Low-speed 1.5 Mbps and Full-speed 12 Mbps USB devices - Root hub integrated with two downstream USB ports - Two embedded USB transceivers
5.7
Ethernet MAC 10/100
The Ethernet MAC acting as an AHB master controls the data exchange between the ethernet channel and the ARM Internal RAM or the external memories. The Ethernet MAC is the hardware implementation of the MAC sub-layer OSI reference model between the physical layer (PHY) and the logical link layer (LLC). It controls the data exchange between a host and a PHY layer according to Ethernet IEEE 802.3u data frame format. The Ethernet MAC contains the required logic and transmits and receives FIFOs for the DMA management. In addition, it is interfaced through MDIO/MDC pins for the PHY layer management. The Ethernet MAC can transfer data through the Reduced Media Independent Interface (RMII). The aim of the interface reduction is to lower the pin count for a switch product that can be connected to multiple PHY interfaces. The characteristics specific to RMII mode are: * Single clock at 50 MHz frequency * Reduction of required control pins * Reduction of data paths to di-bit (2-bit wide) by doubling clock frequency * 10 Mbits/sec. and 100 Mbits/sec. data capability
5.8
mAgicV JTAG
The mAgicV-JTAG provides the JTAG interface to the mAgicV core. It converts JTAG commands coming from a JTAG probe into AHB cycles. Acting as an AHB master it can access all mAgicV memories and registers, thus allowing mAgicV debug software to control the core and its resources: to upload/download data and programs and to configure functional and debug registers.
5.9
External Bus Interface (EBI)
Each enabled AHB master can access the external memory resources through the EBI. The External Bus IF incorporates the Static Memory Controller (SMC) and Synchronous Dynamic RAM controller (SDRAMC). The EBI features: * Eight Chip Select Lines (four via PIO lines) * 26-bit Address Bus (four msb via PIO lines) * 32-bit Data Bus * Multiple Access Modes supported * Byte Write Lines * Programmable Wait State Generation * Programmable Data Float Time * Slow clock mode supported
23
7010AS-DSP-07/07
5.9.1
Static Memory Controller (SMC) The SMC gives to the AHB enabled Hosts the capability to access to the following type of external memories: SRAM, Nor-Flash, EPROM, EEPROM. The additional NAND LOGIC also provides the SMC with the capability to interface the SmartMedia removable non-volatile memory cards and the Nand FLASH memory chips. The additional Compact Flash logic provides the SMC with the capability to interface the Compact Flash removable non-volatile memory cards.
5.9.2
Synchronous Dynamic RAM Controller (SDRAMC) The SDRAMC provides the interface to an external 16-bit or 32-bit SDRAM device. The page size supports ranges from 2048 to 8192 and the number of columns from 256 to 2048. It supports byte (8-bit), half-word (16-bit) and word (32-bit) accesses. The SDRAMC supports a read or write burst length of one location. It does not support byte read/write bursts or half-word write bursts. It keeps track of the active row in each bank (avoiding precharge and active when, changing bank, the old row is accessed), thus maximizing SDRAM performance, e.g., the application may be placed in one bank and data in the other banks. So it is advisable to avoid accessing different rows in the same bank in order to optimize performance. The maximum number of SDRAM locations that can be randomly accessed without penalty cycles (precharge, active) corresponds to the device row size x the number of banks. The SDRAMC can support row size up to 2048 locations and 4 banks: hence maximum 8K locations can be accessed without penalties. Anyway, typical SDRAM row size are 512/256 locations so maximum 2K/1K locations can be accessed without penalties.
5.10
Memory Mapping
The present section describes the memory mapping of ARM9System. Table 5-1 shows the D940HF global memory map:
Table 5-1.
D940HF Global Memory Map
masters
Start Address 0x0000 0000 0x1000 0000 0x9000 0000 0xF000 0000
Size (MB) 256 8 x 256 6 x 256 256
ARM9-I mst # 0
ARM9-D mst #1
PDC mst # 2
magicV mst # 3
USB mst # 4
ETH mst # 5
m-JTAG mst # 6
Internal Memories (See Table 5-3) External Memories (See Table 5-2) Undefined (Abort) Internal Peripherals (See Table 5-4)
24
AT572D940HF Preliminary
7010AS-DSP-07/07
AT572D940HF Preliminary
Table 5-2 shows the external memory mapping: Table 5-2. External Memory Map
masters Start Address 0x1000 0000 0x2000 0000 0x3000 0000 0x4000 0000 0x5000 0000 0x6000 0000 0x7000 0000 0x8000 0000 Size (MB) 256 256 256 256 256 256 256 256 ARM9-I mst #0 ARM-D mst #1 PDC mst #2 magicV mst #3 EBI CS0: EBI CS1: SMC or SDRAMC EBI CS2: SMC EBI CS3: SMC (SmartMedia or NAND-Flash) EBI CS4: SMC (Compact Flash slot 0) EBI CS5: SMC (Compact Flash slot 1) EBI CS6: SMC EBI CS7: SMC USB mst #4 ETH mst #5 m-JTAG mst #6
Table 5-3 shows the internal memory map: Table 5-3. Internal Memory Map
masters
ARM9-I mst # 0 Size (MB) 1 1 1 1 1 1 1 IntROM USB cfg magicV magic V magic V ARM AHB MEM REMAP=0 BMS=1 IntROM BMS=0 EBI NCS0 IntRAM C REMAP=1 ARM9-D mst # 1 REMAP=0 BMS=1 IntROM BMS=0 EBI NCS0 IntRAM C I-TCM D-TCM REMAP=1 PDC mst # 2 magic V mst# 3 USB mst # 4 ETH mst # 5 mJTAG mst # 6
Start Address 0x0000 0000 0x0010 0000 0x0020 0000 0x0030 0000 0x0040 0000 0x0050 0000 0x0060 0000
25
7010AS-DSP-07/07
Table 5-4.
Internal Peripherals Map
masters
Start Address 0xF000 0000 0xFFFA 0000 0xFFFA 4000 0xFFFA 8000 0xFFFA C000 0xFFFB 0000 0xFFFB 4000 0xFFFB 8000 0xFFFB C000 0xFFFC 0000 0xFFFC 4000 0xFFFC 8000 0xFFFC C000 0xFFFD 0000 0xFFFD 4000 0xFFFD 8000 0xFFFD C000 0xFFFE 0000 0xFFFE 4000 0xFFFF 0000 0xFFFF EA00 0xFFFF EC00 0xFFFF EE00 0xFFFF F000 0xFFFF F200 0xFFFF F400 0xFFFF F600 0xFFFF F800 0xFFFF FA00 0xFFFF FC00 0xFFFF FD00 0xFFFF FE00
Size (byte) 40 x 16k 16k 16k 16k 16k 16k 16k 16k 16k 16k 16k 16k 16k 16k 16k 16k 16k 16k 3 x 16k 117 x 512 512 512 512 512 512 512 512 512 512 256 256 2 x 256
ARM9-I
ARM9-D
PDC reserved TC 0, 1, 2 USB DEV MCI TWI-0 USART-0 USART-1 USART-2 SSC-0 SSC-1 SSC-2 SPI-0 SPI-1 SSC-3 TWI-1 ETH CFG CAN-0 CAN-1 reserved reserved SDRAMC SMC HMATRIX AIC DBGU PIO A PIO B PIO C reserved PMC SYSC reserved
magicV
USB
ETH
m-JTAG
26
AT572D940HF Preliminary
7010AS-DSP-07/07
AT572D940HF Preliminary
5.11 APB peripherals
The D940HF provides a rich set of peripherals connected on the APB bus. All enabled AHB masters can access these peripherals through the AHB-APB bridge. 5.11.1 Peripheral ID Table 5-5 defines the Peripheral Identifiers of the D940HF. A peripheral identifier is required for the control of the peripheral interrupt with the Advanced Interrupt Controller and for the control of the peripheral clock with the Power Management Controller. Table 5-5. Peripheral ID
Peripheral Clock Assignment Host Clock Assignment
Peripheral ID 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
PIO A PIO B PIO C ETH APB USART-0 USART-1 USART-2 MCI USB Device TWI-0 SPI-0 SPI-1 SSC-0 SSC-1 SSC-2 TIMER-0 TIMER-1 TIMER-2 USB HOST SSC-3 TW1 CAN-0 CAN-1 ETH AHB
MAGIC Core
27
7010AS-DSP-07/07
Table 5-5.
Peripheral ID (Continued)
Peripheral Clock Assignment Host Clock Assignment
Peripheral ID 29 30 31
5.11.2
Peripheral Multiplexing The D940HF features three PIO controllers, PIOA, PIOB and PIOC, that multiplex the I/O lines of the peripheral set. Each PIO controller manages up to thirty-two lines. Each line can be assigned to one of the two peripheral functions, A or B. Table 5-6 to Table 5-8 define how the I/O lines of the peripherals A and B are multiplexed on the PIO Controllers. Note that some output only peripheral functions might be duplicated within the tables and are indicated with the suffix II and III. PIO A Line Resource Mapping
Periph INPUT A Periph OUTPUT A Periph INPUT B Periph OUTPUT B mAgicV output: M_SIRQ0 EBI: output: CFCE1 (III) EBI: output: CFCE2 (III) CAN 1: dout (III) mAgicV output: M_SIRQ2 TIMER bidir: TIMER_OUT A0 TIMER bidir: TIMER_OUT B1 DBGU output: DTXD(III) PMC output: CKOUT 1 SPI 0 output: CS1 (III) USART 0 output: RTS USART 0 bidir: SCK AIC input: EXT_IRQ1 (also to mAgicV) ETH bidir MDIO ETH output MDC ETH output: FCE100 ETH input: EREFCK ETH input: ECRSDV ETH input: ERX0 ETH input: ERX1 ETH input: ERXER ETH output: ETX0 ETH output: ETX1 AIC input: EXT_IRQ2 (also to mAgicV) TIMER input: TIMER_IN 2 PMC output: CKOUT 0 EBI: output: NCS4/CFCS0 (III) EBI: output: NCS5/CFCS1 (III) EBI: output: NCS6 (III) EBI: output: NCS7 (III) TEST output: m_ck TEST output: a_ck TIMER input: TIMER_IN 1 SPI 0 output: CS2 (III) USART 0 output: RTS (III) mAgicV output: M_SIRQ1
Table 5-6.
PIO A PIO A [0] PIO A [1] PIO A [2] PIO A [3] PIO A [4] PIO A [5] PIO A [6] PIO A [7] PIO A [8] PIO A [9] PIO A [10] PIO A [11] PIO A [12] PIO A [13] PIO A [14] PIO A [15] PIO A [016 PIO A [17] PIO A [18] PIO A [19] PIO A [20] PIO A [21] PIO A [22]
SPI 0 bidir: MISO SPI 0 bidir: MOSI SPI 0 bidir: CLK SPI 0 bidir: CS0 SPI 0 output: CS1 SPI 0 output: CS2 SPI 0 output: CS3 USART 0 input: RXD USART 0 bidir: TXD USART 0 input: CTS
28
AT572D940HF Preliminary
7010AS-DSP-07/07
AT572D940HF Preliminary
Table 5-6.
PIO A PIO A [23] PIO A [24] PIO A [25] PIO A [26] PIO A [27] PIO A [28] PIO A [29] PIO A [30] PIO A [31] EBI input: BMS EBI input: NWAIT EBI output: NCS4/CFCS0 EBI output: NCS5/CFCS1 EBI output: NCS6 EBI output: NCS7 EBI output: CFCE1 EBI output: CFCE2
PIO A Line Resource Mapping (Continued)
Periph INPUT A Periph OUTPUT A ETH output: ETXEN Periph INPUT B Periph OUTPUT B mAgicV output: M_SIRQ0 (III) mAgicV output: M_SIRQ1 (III) USART 2 output: RTS (III) TIMER bidir: TIMER_OUT A2 PMC output: CKOUT 2 EBI output: SMOE EBI output: SMWE PMC output: CKOUT 3 mAgicV output: M_SIRQ3
Table 5-7.
PIO B PIO B [0] PIO B [1] PIO B [2] PIO B [3] PIO B [4] PIO B [5] PIO B [6] PIO B [7] PIO B [8] PIO B [9] PIO B [10] PIO B [11] PIO B [12] PIO B [13] PIO B [14] PIO B [15] PIO B [016 PIO B [17] PIO B [18] PIO B [19] PIO B [20] PIO B [21]
PIO B Line Resource Mapping
Periph INPUT A SSC: RD0 SSC: TD0 SSC: TF0 SSC: TK0 SSC: RF0 SSC: RK0 SSC: RD1 SSC: TD1 SSC: TF1 SSC: TK1 SSC: RF1 SSC: RK1 SSC: RD2 SSC: TD2 SSC: TF2 SSC: TK2 SSC: RF2 SSC: RK2 SSC: RD3 SSC: TD3 SSC: TF3 SSC: TK3 Periph OUTPUT A Periph INPUT B Periph OUTPUT B SPI 0 output: CS3 (III) TIMER bidir: TIMER_OUT B0 PMC CKOUT 0 (II) CAN 0: dout (II) USART 0 RTS (II) mAgicV output: M_SIRQ1 (II) CAN 0: dout (III) TIMER bidir: TIMER_OUT A1 PMC CKOUT 1 (II) SPI 1 output: CS1 (III) USART 1 RTS (III) EBI: A[22] (III) EBI: A[23] (III) mAgicV output: M_SIRQ2 (II) EBI: A[24] (III) SPI 0 output: CS3 (II) ETH output: MDC (II) ETH output: FCE100 (II) EBI: A[25]-CFRNW (III) mAgicV output: M_SIRQ0 (II) ETH output: MDC (III) ETH output: FCE100 (III)
29
7010AS-DSP-07/07
Table 5-7.
PIO B PIO B [22] PIO B [23] PIO B [24] PIO B [25] PIO B [26] PIO B [27] PIO B [28] PIO B [29] PIO B [30] PIO B [31]
PIO B Line Resource Mapping (Continued)
Periph INPUT A Periph OUTPUT A SSC: RF3 SSC: RK3 TIMER input: TIMER_IN 0 AIC input: EXT_IRQ0 (also to mAgicV) CAN 0: din CAN 0: dout EBI: A[22] EBI: A[23] EBI: A[24] EBI: A[25]-CFRNW Periph INPUT B Periph OUTPUT B USART 1 RTS (II) DBGU output: DTXD (II) mAgicV output: M_MODE USART 2 RTS (II) SPI 1 output: CS2 (III) mAgicV output: M_SIRQ3 (II) SPI 0 output: CS1 (II) SPI 0 output: CS2 (II) PMC CKOUT 2 (II) PMC CKOUT 3(II)
Table 5-8.
PIO C PIO C [0] PIO C [1] PIO C [2] PIO C [3] PIO C [4] PIO C [5] PIO C [6] PIO C [7] PIO C [8] PIO C [9] PIO C [10] PIO C [11] PIO C [12] PIO C [13] PIO C [14] PIO C [15] PIO C [16] PIO C [17] PIO C [18] PIO C [19]
PIO C Line Resource mapping
Periph INPUT A Periph OUTPUT A Periph INPUT B Periph OUTPUT B SSC: TD0 (II) SSC: TD1 (II) SSC: TD2 (II) ETH output: ETX0 (II) ETH output: ETX1 (II) mAgicV output: M_SIRQ3 (III) EBI: output: SMOE (III) SSC: TD0 (III) SSC: TD1 (III) SSC: TD2 (III) ETH output: ETX0 (III) ETH output: ETX1 (III) USART 1 RTS USART 1 SCK USART 2 RXD USART 2 TXD USART 2 CTS USART 2 RTS USART 2 SCK TIMER bidir: TIMER_OUT B2 SPI 1 output: CS1 (II) SSC: TD3 (II) EBI: A[22] (II) EBI: A[23] (II) EBI: A[24] (II) EBI: A[25]-CFRNW (II) SPI 1 output: CS2 (II) SPI 1 output: CS3 (II)
SPI 1 bi-directional: MISO SPI 1 bi-directional: MOSI SPI 1 bi-directional: CLK SPI 1 bi-directional: CS0 SPI 1 output: CS1 SPI 1 output: CS2 SPI 1 output: CS3 TWI 0 bi-directional: TWD TWI 0 bi-directional: TWCK USART 1 RXD USART 1 TXD USART 1 CTS
30
AT572D940HF Preliminary
7010AS-DSP-07/07
AT572D940HF Preliminary
Table 5-8.
PIO C PIO C [20] PIO C [21] PIO C [22] PIO C [23] PIO C [24] PIO C [25] PIO C [26] PIO C [27] PIO C [28] PIO C [29] PIO C [30] PIO C [31] DBGU input: DRXD DBGU output: DTXD
PIO C Line Resource mapping (Continued)
Periph INPUT A Periph OUTPUT A Periph INPUT B Periph OUTPUT B SSC: TD3 (III) SPI 1 output: CS3 (III) CAN 1: dout (II) mAgicV output: M_SIRQ2 (III) EBI: SMOE (II) EBI: SMWE (II) EBI: NCS4/CFCS0 (II) EBI: NCS5/CFCS1 (II) EBI: NCS6 (II) CAN 1: dout EBI: NCS7 (II) EBI: CFCE1 (II) EBI: CFCE2 (II)
TWI 1 bi-directional: TWD TWI 1 bi-directional: TWCK MCI bidir: MCCK MCI bidir: MCCDA MCI bidir: MCDA0 MCI bidir: MCDA1 MCI bidir: MCDA2 MCI bidir: MCDA3 CAN 1: din
5.11.3
System Controller (SYSC) The SYSC includes the Reset Controller (RSTC) and the System Timers (SYST). The RSTC manages all system resets: external devices reset, processors reset and peripheral reset. The sources of reset can be: Power-On, Watch Dog, SW reset, External reset. The SYST features: * One 16-bit Period Interval Timer * One 12-bit key-protected Watchdog Timer * One 20-bit Free-running Real-time Timer
5.11.4
Power Management Controller (PMC) The PMC features two clock sources: Slow Clock Oscillator (32.768 Hz) and Main Oscillator (8 to 20 MHz). Two dividers, A and B, and two Phase Lock Loops, A and B, allow a wide range of frequencies to be generated from either the slow clock and/or the main clock. The PMC provides dedicated clocks toward: ARM926, the AHB Matrix, mAgicV, mAgicV Memories, the USB, the Ethernet MAC and all Peripherals.
5.11.5
Advanced Interrupt Controller (AIC) The AIC features: * Controls the interrupt lines (nIRQ and nFIQ) of ARM926 * Thirty-two individually maskable and vectored interrupt sources * Programmable Edge-triggered or Level-sensitive Internal Sources * Programmable Positive/Negative Edge-triggered or High/Low Level sensitive
31
7010AS-DSP-07/07
* 8-level Priority Controller * Fast Forcing: allows redirection of any normal interrupt source on the nFIQ 5.11.6 Parallel Input/Output (PIO) The three PIOs provide globally 96 programmable I/O Lines. These lines are fully programmable through Set/Clear Registers or linked to one of the two peripheral functions. Each I/O Line (assigned to a peripheral or used as a general purpose I/O) provides: * Input change interrupt * Glitch filter * Multi-drive option enables driving in open drain * Programmable pull up on each I/O line * Pin data status register, supplies visibility of the level on the pin at any time 5.11.7 Universal Synchronous Bus Device (USBD) The USB Device provides communication services between an external host and D940HF. The USB device is connected to the APB through a FIFO. The USB Device features: * USB V2.0 full-speed compliant, 12 Mbits per second * Embedded USB V2.0 full-speed transceiver * Embedded dual-port RAM for endpoints * Suspend/Resume logic * Embedded Transceivers 5.11.8 Timer Counter (TC) The TC consists of three 16-bit Timer Counter Channels providing a wide range of functions including: * Frequency Measurement * Event Counting * Interval Measurement * Pulse Generation * Delay Timing * Pulse Width Modulation * Up/down Capabilities Each channel is user-configurable and contains: * Three external clock inputs * Five internal clock inputs * Two multi-purpose input/output signals 5.11.9 Two Wire Interface (TWI) The D940HF provides two independent TWIs.
32
AT572D940HF Preliminary
7010AS-DSP-07/07
AT572D940HF Preliminary
Each TWI interconnects components on a unique two-wire bus, made of one clock line and one data line which speeds of up to 400 Kbits per second, based on a byte oriented transfer format. Each TWI is programmable as a master with sequential or single-byte access. A configurable baud rate generator allows the output data rate to be adapted to a wide range of core clock frequencies. 5.11.10 Universal Synchronous Asynchronous Rx Tx (USART) The D940HF provides three independent USARTs. Each USART features: * Synchronous and Asynchronous mode * Programmable Baud Rate Generator (up to 115.2 Kbps in Asynchronous Mode and system clock frequency in Synchronous Mode) * RS485 with driver control signal * ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards * IrDA modulation and demodulation * PDC connection 5.11.11 Serial Synchronous Controller (SSC) The D940HF provides four independent SSCs. Each SSC provides a programmable serial synchronous communication link to be used in audio and telecom applications (CODECs in Master or Slave Modes, I2S, TDM Buses, Magnetic Card Reader, SPI, ...). The PDC connection allows a direct data transfer between the CODECs and mAgicV data memory, ARM internal memory or external memories. 5.11.12 Serial Peripheral Interface (SPI) The D940HF provides two independent SPIs. Each SPI supports the communication with serial external devices such as DataFlash, ADCs, DACs, LCD Controllers, CAN Controllers and Sensors. Four chip selects with external decoder support allow communication with up to 15 peripherals. The PDC connection allows a direct data transfer between these serial devices and mAgicV data memory, ARM internal memory or external memories. 5.11.13 Debug Unit (DBGU) The DBGU is a 2-wire UART dedicated to Debug Communication. The DBGU TX and RX channels are associated with two PDC channels. The Debug Unit also generates the Debug Communication Channel (DCC) signals provided by the In-circuit Emulator of the ARM processor visible to the software. These signals indicate the status of the DCC read and write registers and generate an interrupt to the ARM processor, allowing the handling of the DCC under interrupt control.
33
7010AS-DSP-07/07
5.11.14
Controller Area Network (CAN) The D940HF provides two independent CANs. Each CAN is fully compliant with the CAN 2.0 Part A and 2.0 Part B. The CAN supports bit/rate up to 1 Mbps.
5.11.15
Multimedia Card Interface (MCI) The D940HF provides a MCI. The MCI has two slots, each supporting: - One slot for one MultiMedia Card bus (up to 30 cards) or - One SD Memory Card The PDC connection allows direct data transfer between these serial devices and mAgicV data memory, ARM internal memory or the external memories.
34
AT572D940HF Preliminary
7010AS-DSP-07/07
AT572D940HF Preliminary
6. Mechanical Drawing
Figure 6-1. 324-ball CABGA Package Drawing (dimensions in mm)
35
7010AS-DSP-07/07
7. Power Dissipation
The D940HF has six kinds of power supply pins: * VDDCORE pins, which power the chip core (1.1V / 1.2V) * VDDOSC32 pins, which power the 32KHz oscillator cell (1.1V / 1.2V) * VDDOSCM pins, which power the main oscillator cell (1.1V / 1.2V) * VDDIOM pins, which power the EBI I/O lines (3.3V) * VDDIOP pins, which power the Peripheral I/O lines (3.3V) * VDDPLLA pins, which power the PLLA cell (3.3V)
7.1
Power Consumption
The D940HF consumes about 2mA in typical conditions of static current VDDCORE. For dynamic power consumption the D940HF consumes about 300mA in typical conditions at maximum working frequencies with a 20% toggling rate.
36
AT572D940HF Preliminary
7010AS-DSP-07/07
AT572D940HF Preliminary
8. Ordering Guide
Table 8-1. Ordering Information
Temp. Range 0C to 70C Speed Grade (Max) 160 MHz Operating Voltage 3.3V (I/O) 1.1V (core) 1.8V-2.5V-3.3V (I/O) 1.2V (core) 1.8V-2.5V-3.3V (I/O) 1.2V (core) Package CA324BGA (RoHS) CA324BGA (RoHS) CA324BGA (RoHS) Notes Full Peripheral Set Reduced Periperal Set (1) Full Peripheral Set Status Sampling Contact: diopsis@atmel.com Contact: diopsis@atmel.com
Part Number AT572D940HF
AT572D940HF-CL
0C to 70C
160 MHz
AT572D940HF-CJ 1.
-40C to 85C
200 MHz
Some peripherals are not accessible by the user in this low-cost version. Reduced Peripheral Set = Full Peripheral Set - 2 CANs -3 SSCs - 1 SPI - 1 TWI - 2 USARTs. Consequently the related PIO lines can be used only as SW controlled PIO lines (not linked to any peripherals).
37
7010AS-DSP-07/07
9. Revision History
Doc. Rev. 7010AS Date 07/07 Comments
* Initial document release
38
AT572D940HF Preliminary
7010AS-DSP-07/07
Headquarters
Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
International
Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581
Product Contact
Web Site www.atmel.com Technical Support diopsis@atmel.com Sales Contact www.atmel.com/contacts
Literature Requests www.atmel.com/literature
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.
(c) 2007 Atmel Corporation. All rights reserved. Atmel(R), logo and combinations thereof, DIOPSIS (R), DataFlash (R) and others are registered trademarks, Magic DSP TM and others are trademarks of Atmel Corporation or its subsidiaries. ARM (R), Thumb (R) and others are the registered trademarks or trademarks of ARM Ltd. Other terms and product names may be trademarks of others.
7010AS-DSP-07/07

▲Up To Search▲

Price & Availability of AT572D940HF

	To Download AT572D940HF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .